1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device, suitable for the fabrication of a heterojunction bipolar transistor.
2. Description of the Prior Art
FIG. 3 shows a cross section of a heterojunction bipolar transistor. The heterojunction bipolar transistor shown has a layered structure consisting of a sub-collector layer 1, a collector layer 2, a base layer 3, an emitter layer 4, and an emitter contact layer 5, the layers being formed one on top of another on a semiconductor substrate 6 in the order named.
On the upper surface of the base layer 3 are formed an emitter mesa 50 having a mesa structure and a base electrode 12b. The base electrode 12b is disposed adjacent to the side wall of the emitter mesa 50 with a gap of about 100 nm provided therebetween. An emitter electrode 13 is formed on top of the emitter contact layer 5, while a collector electrode 14 is provided on the sub-collector layer 1.
Referring now to FIGS. 2A to 2C, we will describe a prior art method for the fabrication of the heterojunction bipolar transistor shown in FIG. 3. The prior art method described below involves self-aligning the base electrode 12b to the sidewall of the emitter layer 7 having a mesa structure. This method permits high-density integration of bipolar transistors and lends itself to increasing the speed of transistor operation.
As shown in FIG. 2A, a sub-collector layer 1, a collector layer 2, a base layer 3, an emitter layer 4, and an emitter contact layer 5 are grown one on top of another on a semiconductor substrate 6 using an epitaxial growth technique. After that, a dummy layer 7 is deposited on the emitter contact layer 5. The dummy layer 7 will be removed in the end and will not be used to form the heterojunction bipolar transistor. After patterning the dummy layer 7 in the form of a mesa, the emitter contact layer 5 and the emitter layer 4 are etched, using the patterned dummy layer 7 as the etching mask, to form an emitter mesa 50 while exposing a portion of the base layer 3.
Next, as shown in FIG. 2B, using the dummy layer 7 and a resist pattern 19 as the mask, a base electrode material 12a is deposited on the exposed portion of the base layer 3 as well as on the mask.
By removing the resist pattern 19 and the unwanted base electrode material 12a deposited thereon, a base electrode 12b can be formed in self-alignment to the sidewall of the emitter mesa 50 (FIG. 2C). At this step, however, the base electrode material 12a remains unremoved on the dummy layer 7.
Next, a surface planarization resist (surface smoothing film) 21 is applied over the semiconductor substrate 6 in such a manner as to cover the dummy layer 7, the base electrode material 12a remaining thereon, etc. In the subsequent etch-back process using a dry etching technique, the surface planarization resist 21 is uniformly etched from the surface thereof, thereby exposing a portion of the dummy layer 7 and the base electrode material 12a deposited thereon (FIG. 2C).
Next, using a wet etching technique, the dummy layer 7 is etched away, as a result of which the base electrode material 12a on the dummy layer 7 is lifted off. An emitter electrode material is then deposited over the entire upper surfaces of the emitter contact layer 5 and the surface planarization resist, after which the surface planarization resist and the unwanted emitter electrode material deposited thereon are removed by a lift-off technique, thereby forming an emitter electrode 13 on top of the emitter contact layer 5. Thereafter, using a known technique, selected portions of the base layer 3, collector layer 2, and sub-collector layer 1 are etched away to form a collector electrode 14 on the sub-collector layer 1, thus completing the fabrication of the heterojunction bipolar transistor shown in FIG. 3.
However, in the above prior art process, the upper surface of the dummy layer 7 is completely covered with the base electrode material 12a, as shown in FIG. 2C, when etching the dummy layer 7. Therefore, in order to remove the dummy layer 7 by etching, the etchant must be applied to the dummy layer 7 through an overetched portion 15 in the surface planarization resist 21. Such a method requires a relatively long etching time (e.g., about 10 minutes) to etch away the dummy layer 7 and remove the base electrode material 12a on the dummy layer 7. A long etching time may result in the stripping of the surface planarization resist 21. Since the surface planarization resist 21 is usually composed of organic resist, if it suffers plasma damage during the dry etching in the etchback process, etc., it will lose resistance to the etchant (e.g., buffered hydrofluoric acid) applied to the dummy layer 7. If stripping is caused to the surface planarization resist 21 during the process of removing the dummy layer 7 by etching, deposition of emitter metal may cause a short circuit between the base and the emitter. As a result, the prior art has had difficulty in producing heterojunction bipolar transistors with high fabrication yield.